thanks.

Just finished the RISC-V optimization sprint for Milk-V Mars (SiFive U74). Using U74-specific in-order scheduling gave us a 34% boost in verification speed. This is part of the v3.11 roadmap to make UltrafastSecp256k1 the go-to library for resource-constrained IoT devices. Cycles don't lie! 🚀

thanks for your support and effort :)

https://github.com/shrec/UltrafastSecp256k1/commit/1a9cebc3ba703f87ce03d09e95a4aec8f1a06f4a#commitcomment-177853124 :)

Haha, fair enough! While I'm busy optimizing the next +51% speedup for v3.11, I’ll let the code and the commits speak for my identity.

If you want proof that I’m the one pushing these 5x52 field representation assembly bypasses, check the latest signed commit on GitHub or look out for the RISC-V (Milk-V Mars) benchmarks I’m about to drop.

Instead of zapping back, I’d rather you use those sats to support other open-source devs or run a benchmark of UltrafastSecp256k1 on your own node. Let the cycles do the talking! 🚀

Thank you for the support and the sats, @0xbitcoiner and everyone!It’s exciting to see the community take interest in these optimizations. Our team has been working around the clock to push the boundaries of $secp256k1$ performance, especially for high-throughput environments.We just hit a major milestone with v3.10.x, achieving a +51% speedup in constant-time generator multiplication on x86-64 and significant gains on ARM64, all while passing 12,023 consistency tests.We are now focusing on v3.11, which will bring further refinements to Field Inversion and expanded hardware support for RISC-V. Feedback from this community is invaluable—feel free to dig into the code or the benchmarks on our GitHub.🚀 Onward to more speed and security!